A synthesis-oriented VHDL course

dc.contributor.author	d’Amore Roberto
dc.date.accessioned	2018-02-05T14:33:49Z
dc.date.available	2018-02-05T14:33:49Z
dc.date.issued	2010
dc.identifier.uri	http://hdl.handle.net/123456789/7118
dc.description.abstract	This article proposes a VHDL language course that establishes a strong correlation between the language statements and their use in circuit synthesis. Two course modules are described: a basic module that contains the essential concepts of the language, sufficient for students to describe medium complexity circuits, followed by a second module with more complex language concepts. The benefits of correlated laboratory tasks which use simulation and synthesis tools are discussed. Evaluation content, student test scores, and student feedback are presented. Suggestions for improving and modifying the course are given.
dc.format	application/pdf
dc.language.iso	English
dc.publisher	Association for Computing Machinery (ACM)
dc.subject	System Verilog, SystemC, VHDL, Verilog, digital course
dc.title	A synthesis-oriented VHDL course
dc.type	journal-article
dc.identifer.doi	10.1145/1789934.1789936
dc.source.volume	10
dc.source.issue	2
dc.source.journal	ACM Trans. Comput. Educ